1. Field of the Invention
The present invention relates to circuit and method for timing recovery in a digital communication receiver of a direct sequence spread spectrum(DSSS) type in which a period of symbol transmitted from a transmitter is predicted for tracking a position of a despread symbol in samples from each period.
2. Background of the Related Art
In a direct sequence/code division multiple access(DS/CDMA) system, a data is directly spread by means of a PN(Pseudo Noise) code before transmission, and a receiver generates a PN code having the same phase with a phase of a transmitter PN code to despread a received, spread spectrum signal, for recovering the received signal. Current analog mobile communication system of which subscriber capacity has been saturated is under replacement with a digital mobile communication system, because the DS/CDMA system allows a high security of communication as detecting of presence of signal is difficult and, even if the presence of signal is known, recovering of an exact signal without knowing the PN code is difficult, and because detection of desired signal only is possible, which allows multiple access and a large subscriber capacity, even if the same carriers are used in signal transmission and reception as users use their own PN codes. However, the DS/CDMA system has to have a PN synchronization for matching phases of the PN codes in the transmitter and the receiver, for which a symbol timing recovery circuit is provided to the receiver.
In the symbol timing recovery circuits, there are an open-loop synchronizer and a closed-loop synchronizer. FIG. 1 illustrates a related art symbol timing recovery circuit of an open-loop synchroniser in a digital communication receiver.
Referring to FIG. 1, the related art symbol timing recovery circuit of an open-loop synchroniser in a digital communication receiver is provided with a power calculation circuit 11 for calculating an output of the matched filter 10 to provide a power signal, a threshold circuit 12 for comparing an output of the power calculating circuit 11 with a preset threshold value to generate pulses when the output exceeds the threshold value, a band pass filter(BPF)13 for filtering an output of the threshold circuit 12, and a zero detection circuit 14 for detecting a zero crossing of a signal from the band pass filter 13 to provide a symbol clock, so that an output of the zero detection circuit 14 drives a sampler 15 and a baseband demodulator 16, in the receiver synchronizing circuit, for providing a sustained signal s(n), which sustains a symbol value selected as a symbol from samples from the matched filter 10 for a symbol period, and a signal d(n) demodulated by the base band demodulator 16. The matched filer 10 may be a correlator of a tapped-delay type or an integrated-dump type having a PN code stored in a shift register. Explanation of the related art hereafter is based on the correlator of a tapped-delay type. FIG. 2 illustrates a power signal m.sub.p (k) from the power calculation circuit 11, which calculates an output of the matched filter 10 into power without noise, wherein a number of samples per symbol can be expressed as C.times.K(=S), where C denotes a number of PN code chips per symbol and K denotes a number of samples per chip. In general, a function of the timing recovery circuit in the spread spectrum system is extractions from a received signal, of C.times.K, a symbol period, and a despread value from a C.times.K number of samples in each symbol period, i.e., a sample period more or less having a maximal power, as the power will be maximum when the PN codes both in the receiver, and transmitter sides are synchronized.
FIGS. 3a.about.3c illustrate waveforms at different output terminals of 11.about.15 shown in FIG. 1 for explaining the operation of the open-loop type synchronizer.
Referring to FIG. 3a, the power calculation circuit 11 uses an output m(k) of the matched filter 10 in calculating power m.sub.p (k) in each sample period. In this instance, of the power signals m.sub.p (k), a maximal power of a third symbol is below the threshold value due to degradation of an output of the matched filter 10 caused by a noise. The threshold circuit 12 receives a power of each sample period, compares to a preset threshold value, and provides a high level signal when the power exceeds the threshold value. Therefore, since the third symbol has a maximal power value below the threshold value, no high level signal is provided. Then, as shown in FIG. 3c, the BPF 13 filters outputs of the threshold circuit 12 and provides a high level output at a position of a symbol period which does not exceed the threshold value using a proximate symbol period known in the receiver. Then, as shown in FIG. 3d, the zero detection circuit 14 detects a zero crossing from outputs of the BPF 13 and provides a symbol clock to the sampler 15 and the demodulator 16 as a symbol timing, thereby making a PN synchronization of the phases of codes of the transmitter and the receiver.
And, referring to FIG. 4, in a timing recovery circuit in a digital communication receiver provided with a matched filter for received signal r(k) from a transmitter and correlating the received signal r(k) with a PN code delayed for a sample interval, an on sampler 21 for sampling an output m(k) of the matched filter 20, and a demodulator 22 for demodulating an output s(n) of the on sampler 21, for detecting a sample period which has a maximal power value from a symbol from the matched filter and for setting as a driving timing for the on sampler 21 and the demodulator 22, the related art closed-loop synchronizer is provided with a power calculation circuit 23 for receiving an output m(k) of the matched filter 20 and calculating a power, an early sampler 24 operative at a sample period earlier than the on sampler 21 for receiving an output m.sub.p (k) of the power calculation circuit 23 and providing at a sample period earlier than the on sampler 21, a late sampler 25 operative at a sample period later than the on sampler 21 for receiving an output m.sub.p (k) of the power calculation circuit 23 and providing at a sampler period later than the on sampler 21, an adder 26 for adding a difference of outputs of the earlier sampler 24 and the late sampler 25, a low pass filter 27 for filtering outputs of the adder 26 to pass a low frequency portion only, and a digital control oscillator(DCO) 28 for receiving an output of the low pass filter 27, providing an early clock, a late clock, and a symbol clock, and driving the early sampler 24, the later sampler 25, the on sampler 21, and the demodulator 22 by means of respective clocks. The DCO 28 is provided with a general modulo accumulator.
The operation of the aforementioned closed-loop synchronizer will be explained with reference to FIG. 5.
Referring to FIG. 5a, the power calculation circuit 23 receives an output m(k) of the matched filter 20 and calculated a power of the PN code. A third symbol of the output signals m.sub.p (k) has a maximal power value lower than a reference value due to an external noise. Then, upon receiving the output m.sub.p (k) of the power calculation circuit 23, the early sampler 24 extracts a power signal earlier than the on sampler 21 and the late sampler extracts a power signal later than the on sampler 21. The adder 26 generates a signal of an output difference of the early sampler 24 and the late sampler 25 and provides the difference to the DCO 28 through the low pass filter 27. The DCO 28 accumulates the received output difference on a predetermined accumulation unit. FIG. 5b illustrates a change of value in a modulo accumulator in the DCO 28. As shown in a first symbol period in FIG. 5a, a time(a number of clocks) for obtaining a maximal value in the accumulator is prolonged in a case when an output difference of the early sampler and the late sampler is negative because the accumulation unit decreases as the output difference is subtracted from the basic accumulation unit, and for a second symbol period shown in FIG. 5a, a time for obtaining a maximal value in the accumulator is shortened in a case when an output difference of the early sampler 24 and the late sampler 25 is positive because the accumulation unit increases as the output difference is added to the basic accumulation unit. As shown in FIG. 5c, if a threshold value is set to an accumulator value to provide a clock every time the accumulator value exceeds the threshold value, three symbol timings of the early clock, the symbol clock, and the late clock are generated. And, the early clock and the late clock are adapted to drive the early sampler 24 and the late sampler 25 respectively, and the symbol clock timing is adapted to drive the on sampler 21 and the demodulator 22. Therefore, since a timing of the symbol clock can be set by detecting a state of a maximal value of the PN code from the matched filer 20 from timings of the early clock and the late clock before and after the symbol clock that is the driving timing of the on sampler, the related art closed-loop synchronizer can improve a BER performance better than the related art open-loop synchronizer.
In conclusion, through the aforementioned open-loop synchronizer of the timing recovery circuit is favorable in making a data transmission rate faster because the open-loop synchronizer has a simple system and no feedback component, the open-loop synchronizer has a disadvantage in that it has a low BER performance, whereas, though the related art closed-loop synchronizer can improve the BER performance, the closed-loop synchronizer has disadvantages in that the closed-loop synchronizer has a complicated system and feedback components, impeding application of a pipeline structure thereto for improving the data transmission rate. Moreover, the timing recovery circuit both of the open-loop synchronizer and the closed-loop synchronizer require a digital filter, which causes a problem in that a user is required to set an optimal pass band according to a channel ambient and carrier frequency(an offset) as the BER performance is dependent on the digital filter and the pass band, significantly.